A semiconductor wafer that is processed in LSI device fabrication process is repeatedly subjected to a high temperature heat treatment in fabrication steps such as oxidation, diffusion and film deposition. In such a heat treatment, if an inhomogeneous temperature distribution should be generated within a wafer surface, the thermal stress is incurred thereby.
Meanwhile, depending on the supporting method, the stress attributable to a wafer weight (hereinafter referred to as tare stress) generates. With regard to a conventional heat treatment boat, said tare stress affects very much in case that the heat treatment is conducted for semiconductor wafers of 300 mm in diameter, thus resulting in making defects-laden products not to be usable.
Both thermal stress and tare stress as above are known to cause crystal defects called slips within semiconductor wafers during heat treatments. The slips end up in an increase of a leakage current in LSI device and/or deterioration of planarity of semiconductor wafers. In order to secure quality as semiconductor wafers, it is important to reduce the tare stress as well as thermal stress in suppressing the generation of slips.
In a heat treatment of semiconductor wafers, a vertical heat treatment furnace can reduce an installation space and is suitable for simultaneously heat treating a large quantity of semiconductor wafers with large diameter, and, accordingly, is adopted in various heat treatments of semiconductor wafers.
FIG. 1 is a diagram showing a configuration example of a heat treatment boat for semiconductor wafers for use in a vertical heat treatment furnace. A heat treatment boat 1 comprises three or more pillars 3, top and bottom panels 5, 6 for fixing said pillars 3 at top and bottom positions, and an opening segment 2. The pillars 3 are provided with a wafer support section 4, so that, after the semiconductor wafers are loaded through the opening segment 2 onto the wafer support section 4, the boat is installed into the vertical heat treatment furnace, being followed by predetermined heat treatment.
As shown in FIG. 1, a heat treatment boat 1 is composed of a pair of top and bottom panels 5, 6 disposed with a space and a plurality of pillars 3 that link these top and bottom panels, thus an opening segment 2 is indispensably provided to charge the semiconductor wafers onto the wafer support section 4 or to discharge those therefrom.
Accordingly, two pillars 3 disposed at the opening segment 2, in order to facilitate charging or discharging of semiconductor wafers, are normally put in place with a space equivalent to the diameter of semiconductor wafer.
With regard to a heat treatment for semiconductor wafers with small diameter, a heat treatment boat shown in above FIG. 1 is used where a plural-point-supporting system as much as three- or four-point-support at the peripheral region of wafer backside is widely applied.
Nonetheless, as the diameter of semiconductor wafers increases recently, the incurred tare stress tends to be increased notably, thereby aggravating an inhomogeneous distribution of tare stresses in case of a heat treatment boat shown in above FIG. 1 where a three- or four-point supporting system is applied at the peripheral region of the wafer backside, and thus resulting in generation of slips markedly.
Accordingly, in order to suppress the generation of slips in association with the increase of diameter of semiconductor wafers, either a jig to support a semiconductor wafer at a plurality of points in the central region of the wafer backside, or a jig structure enabling a semiconductor wafer to make a line or plane contact in a ring-type manner is proposed.
For instance, in Japanese Patent Application Publication No. 10-270369, a wafer supporting jig with a ring-type structure (horse-shoe) having recess portions on its surface, which can be connected to either outward or inward peripheral region, or having a plurality of through-holes is disclosed. According to said supporting jig, it is recognized that an atmosphere gas surrounding an outward peripheral region of said supporting jig is adsorbed during the mobilization of wafers, and the gas is carried to the very contact portion via a plurality of recess portions or through-holes, thereby preventing wafers to adhere to the supporting jig.
Also, in Japanese Patent Application Publication No. 11-3865, a boat for loading wafers is proposed, wherein one pair or plural pairs of beams—a pair of beams being consisted of two beams—is horizontally disposed in the longitudinal direction of the pillars with a predetermined space. By adjusting a space between the two beams, the deflection of wafers is reduced as low as possible, thereby preventing the generation of slips.
Furthermore, in Japanese Patent Application Publication No. 10-321543, a wafer supporting body where a surface roughness is specified is proposed to prevent a silicon wafer from closely adhering to a wafer supporting body (a heat treatment jig) having a disk-type structure or a horse-shoe structure.
Nonetheless, the concerns newly arise in using a heat treatment jig which adopts an improved method of contacting with wafers, such as a proposed supporting jig. Namely, due to the contact of the wafer backside on the supporting jig, the deformation of each component is restricted, whereby the large stress exceeding thermal stress or tare stress will be newly exerted into the semiconductor wafers, thus resulting in generation of slips.
The cause of generating above unexpected slips is considered to be the machining accuracy of the heat treatment jig itself, which particularly hinges on surface planarity and surface roughness on the region where the semiconductor wafer backside contacts with the supporting jig.
However, in case of the supporting jigs and the like which are proposed in Japanese Patent Application Publication Nos. 10-270369, 11-3865 and 10-321543, although there is a description in part regarding surface roughness, there is made neither explanation about its relationship with the slip reduction nor description on surface flatness of the supporting jigs and the like.
Meanwhile, in Japanese Patent Application Publication No. 2003-197722, a ring-type heat treatment jig (including horseshoe-like) is disclosed, wherein surface roughness and flatness are stipulated, and wherein the configuration of said jig is made in such a way that a plurality of through-holes are concentrically disposed over the supporting surface for wafers and a total section area of said through-holes is specified. In above-cited publication, it is taught that preferable surface roughness Ra value and flatness are 0.1-0.7 μm and 50 μm respectively.
In this regard, in considering the heat treatment jig for semiconductor wafers of 300 mm in diameter, high accuracy machining must be applied to secure 50 μm of flatness on whole region to support wafers, thus ending up in the increase of manufacturing cost, which cannot be practical manufacturing parameters in terms of machining accuracy.